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Automotive teams need a verification flow that can keep pace with complex chips, large software stacks and vehicle-level interactions before silicon is committed. Simulation remains useful, but on large multicore systems it may be too slow to run enough software and system tests in time. Hardware emulation can help close that pre-silicon gap, provided OEMs and suppliers share requirements and evidence across the chip-to-vehicle development chain.
Why automotive verification is becoming harder
Cars increasingly depend on electronics and software to meet performance, safety, emissions and fuel-efficiency requirements. Verification is therefore not a single chip test at the end of design: it must establish that components, software, subsystems and the complete vehicle work together correctly.
Responsibility is spread across original equipment manufacturers (OEMs), Tier 1 suppliers that integrate major systems, and Tier 2 suppliers that provide chips and components. As Jean-Marie Brunet, then senior marketing director for Mentor’s Emulation Division, put it in a 2020 article, the shared challenge is proving that electronics and software will run “smoothly, correctly, efficiently, and safely.” That proof depends on requirements and verification evidence moving between organizations, not remaining isolated within each supplier.
More capable chips mean more interactions to test
Automotive silicon has moved beyond small, single-purpose electronic control units toward platform systems-on-chip (SoCs) with numerous CPUs, advanced protocols, vision processing and AI engines. They must also operate within power constraints. Tier 1 suppliers add substantial software stacks, so the verification problem includes both the silicon and its behavior with software and other subsystem components.
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Every interface creates another place where assumptions can fail: protocols must work across implementations, software layers must use hardware correctly, and modules must behave as expected in combination. Broad use cases make that difficult even for the Tier 2 component supplier; integration across several components and software layers adds further risk for Tier 1s.
Vehicle behavior expands the test space
At the vehicle level, scenarios include interactions with other vehicles, pedestrians and other objects in the environment. Digital-twin models—models that mirror individual cars in operation—can extend verification from a chip or subsystem toward a complete automobile. But the number and complexity of scenarios make it challenging to execute verification suites at every level.
Why simulation alone may leave a pre-silicon gap
Software simulation is valuable for checking designs, but it can become impractical when asked to run large multicore SoCs and their software at scale. The 2020 EE Times article by Brunet noted that even simulating an operating-system boot and low-level drivers on enormous multicore chips could take too long for complete verification by simulation alone. The same article described a fundamental gap between the pre-silicon verification required and what simulation could feasibly execute.
There is also a schedule and cost consequence. The article said a complex SoC mask set—the masks used to manufacture the design—could cost millions of dollars, without specifying a more precise figure. Changes made before mask commitment cost engineering time; changes after commitment can require another mask set. The practical goal is to uncover more integration and software issues while the design can still be changed without that additional manufacturing step.
Simulation and hardware emulation: different roles
Hardware emulation runs a design on specialized hardware rather than executing the whole design as a software model. In the automotive flow described by Siemens and Mentor in 2020, emulation is intended to make long-running hardware and software verification workloads practical before silicon exists. It complements simulation rather than making every simulation unnecessary.
| Verification need | Software simulation | Hardware emulation |
|---|---|---|
| Execution speed | Can be too slow for extensive OS, driver and multicore testing at the scale described in the 2020 EE Times article. | Siemens/Mentor described PAVE360 verification suites as running thousands of times faster than standard simulation in its 2020 article; this is a vendor claim, not a general benchmark for every design or workload. |
| Design visibility and debug | Simulation provides a software-model environment for examining behavior. | The PAVE360 description included internal visibility and debug; the 2020 source did not quantify or compare the two approaches’ debug capabilities. |
| Running real software | Can run software against the simulated design, but runtime may limit how much can be exercised on large SoCs. | Hardware/software co-verification was a stated PAVE360 capability; the source did not specify which production software or operating systems were supported. |
| Chip-to-vehicle scenarios | Can contribute models and tests at different abstraction levels; the cited account did not establish a specific simulation-only chip-to-vehicle workflow. | PAVE360 was presented as spanning individual chips, subsystems and full-vehicle verification, with TLM and FMI support for inter-component and electromechanical work. |
| Performance, bandwidth and power | The cited account did not state whether or how these measures were available in simulation. | Hardware/software co-verification with performance, bandwidth and power metrics was among the capabilities claimed for PAVE360. |
| Pre-silicon schedule risk | Long runtimes can restrict how much verification is completed before mask commitment. | Emulation is intended to enable more pre-silicon testing; it cannot guarantee that all defects will be found or eliminate later validation. |
The choice is not simply “simulation or emulation.” Teams can use simulation where it is effective and bring emulation into the flow when runtime, software execution or cross-level integration becomes a bottleneck. Which tests belong in each environment depends on the design, available models and verification objectives; the 2020 source does not provide a universal allocation rule.
How PAVE360 was positioned in the automotive flow
Siemens/Mentor described PAVE360 in 2020 as a chip-to-vehicle verification environment built around Veloce hardware emulation. Its stated scope extended from an individual chip through a subsystem to the full vehicle, with hardware/software co-verification and interoperability with chip, software and post-silicon checkout tools.
Connect components and vehicle models
The account identified transaction-level modeling (TLM) for inter-component verification and the Functional Mock-up Interface (FMI) for electromechanical verification. These interfaces can help teams connect models and verification work across disciplines. They do not, on their own, ensure that models are accurate, requirements align, or evidence is accepted by every organization.
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The vendor description also included functional verification, internal visibility and debug, and measurement of performance, bandwidth and power during hardware/software co-verification. It characterized PAVE360 verification suites as running thousands of times faster than standard simulation. That speed figure is a claim from the 2020 Siemens/Mentor account; it should not be treated as a current, independently verified result for all configurations. The available account does not establish current product availability or present-day performance.
How OEMs, Tier 1s and Tier 2s can share verification evidence
Efficient verification depends on a traceable chain from a system requirement to the component that implements it and the test evidence showing its behavior. The 2020 EE Times account describes closer requirements, verification and validation collaboration between Tier 1 and Tier 2 suppliers, alongside more efficient sharing of intellectual property.
- Make requirements traceable. Identify which component or subsystem owns each requirement and how its implementation is verified.
- Verify interfaces across implementations. Treat protocols and interfaces as shared obligations, not just as internal details of one supplier’s component.
- Reuse relevant evidence. Let Tier 1 integrators and OEM teams assess supplier test results in the context of their own software layers and system scenarios, rather than assuming component-level success proves vehicle-level behavior.
- Keep integration tests at the right levels. Component evidence cannot replace subsystem integration, and subsystem tests cannot cover every interaction with the vehicle environment.
Supply-chain roles are also changing. Brunet’s 2020 article cited Google, Uber, Lyft and Tesla as examples of nontraditional or vertically integrated participants, alongside established suppliers NXP and Nvidia. The point is not that all organizations follow one model, but that design ownership and integration boundaries can shift. A verification process needs clear responsibility and evidence handoffs even when those boundaries do not match a traditional supplier chain.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What ISO 26262 means for verification planning
The 2020 EE Times article characterizes OEMs as ultimately responsible for safety requirements across the subsystems, components and tools used to assemble the final system. In practice, that makes safety-related verification a planning and evidence task across organizational boundaries: testing must be accompanied by documentation and certification work, not treated as an isolated engineering activity.
Best Value
Suppliers need to provide evidence relevant to their components, while integrators must understand how those components contribute to system behavior. The cited article describes extensive planning, testing, documentation and certification, but does not specify clause-level obligations or prescribe a universal evidence package. Teams should use the applicable ISO 26262 edition and project-specific safety process to determine those details.
A practical way to close the verification gap
- Map the system and its owners. Identify the SoC, software layers, subsystem interfaces and vehicle-level scenarios, along with the OEM, Tier 1 or Tier 2 responsible for each.
- Connect requirements to tests and evidence. Track how each requirement is implemented, where it is tested and what results must pass to the next integrator.
- Choose simulation or emulation by workload. Keep simulation for appropriate design checks; consider emulation when multicore execution, software bring-up or test runtime limits the useful coverage achievable before silicon.
- Verify across abstraction levels. Cover component interfaces, subsystem interactions and relevant vehicle scenarios. Do not treat a successful chip test as proof of complete-vehicle behavior.
- Preserve safety and integration records. Maintain the planning, test documentation and certification evidence needed to support the project’s ISO 26262 process.
Efficient verification is therefore not just a faster tool. It is a connected flow that lets teams exercise more of the intended system before tapeout and carry understandable evidence from component suppliers through integration to the vehicle program.
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