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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallHonda and Renesas are developing a high-performance system-on-chip (SoC) for future Honda 0 Series software-defined vehicles (SDVs). The January 2025 announcement describes a planned design—not a finished chip—with targets of 2,000 TOPS and 20 TOPS/W. Honda said it intended the SoC for 0 Series models launching in the late 2020s; final specifications and a confirmed delivery milestone have not been announced in the cited materials.
What Honda and Renesas are developing
The companies signed a development agreement announced on January 8, 2025, at CES 2025. Their goal is an SoC for a high-performance core electronic control unit (ECU) in future Honda 0 Series electric vehicles. An SoC integrates computing functions into a chip or chip package; in this plan, it is intended to help centralize processing for multiple vehicle systems.
Honda describes the intended workload as spanning automated driving and advanced driver-assistance systems (ADAS), powertrain control, and comfort functions. That breadth is central to the SDV idea: vehicle functions can depend on computing and software that Honda expects to evolve over time, rather than being confined to separate, narrowly defined controllers.
How the planned chip is designed
The proposed architecture pairs Renesas’s general-purpose Gen 5 R-Car X5 SoC series with a Honda-optimized AI accelerator. The companies say the design will use multi-die chiplet technology and TSMC automotive 3-nm process technology. These are announced design choices; the release does not provide final production specifications.
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In a chiplet approach, multiple dies with different functions are combined in one package. Honda and Renesas say this can support customization and later functional or performance upgrades. The joint announcement states that chiplet technology “allows flexibility to create customized solutions and offers future upgrades for functional and performance improvements.” That is a stated design rationale, not evidence that a particular post-launch upgrade has been delivered.
What 2,000 TOPS and 20 TOPS/W mean
TOPS means trillions of operations per second, a way to express computing throughput. Honda and Renesas announced a target of 2,000 TOPS for AI performance, based on a sparse AI model. Renesas identified the figure as its estimate as of January 2025. The companies also announced a 20 TOPS/W power-efficiency target.
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Both numbers are targets for the planned design, not independently measured results from a production chip. TOPS alone does not establish how well a system performs real-world driving tasks: results depend on the workload and model, and the figure here is specifically qualified by its sparse-model basis. The announcement does not give a detailed benchmark method or final power measurement conditions, so comparisons with other chips should account for those missing details rather than treating the raw TOPS figure as a complete measure of driving capability.
When Honda expects the SoC in vehicles
Honda’s January 2025 release said the SoC was intended for Honda 0 Series models launching in the late 2020s. That is the stated vehicle-use plan, not confirmation that a particular production model will use a chip with finalized specifications.
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Honda’s broader SDV overview, current as of January 2025, described global launches of Honda 0 Series models starting in 2026. It distinguished the initial models’ domain-centralized architecture from a later-generation plan for a single high-performance central ECU. These milestones describe Honda’s wider vehicle-computing roadmap and should not be conflated with the late-2020s target for the Renesas SoC. The cited materials do not establish the Renesas project’s current milestone status or a confirmed delivery date.
Where the SoC fits in Honda’s SDV strategy
Honda presents the Renesas project as part of a broader software-defined vehicle strategy involving ASIMO OS, over-the-air (OTA) updates, and centralized vehicle computing. A central computing platform can provide a place to coordinate functions that otherwise might be handled across multiple controllers; software and OTA updates are part of Honda’s stated approach to evolving vehicle behavior after launch. The SoC is one planned hardware component of that strategy, not the whole SDV system.
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Honda’s January 2025 overview forecast that SDV AI-performance requirements would be 500 times higher by 2030 than in 2024. This is Honda’s forecast, not an independently verified industry measurement.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to compare this announcement with other automotive chips
The announcement does not establish that this design leads the market. A useful comparison needs more than a peak TOPS figure:
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- Intended role: Which vehicle functions and ECU responsibilities is the chip meant to support?
- Target or achieved: Is the performance a design target, an estimate, or a measured production result?
- Workload basis: What model and benchmark conditions underpin the TOPS figure, including whether sparsity is assumed?
- Efficiency basis: How is TOPS/W measured, and under what operating conditions?
- Manufacturing and integration: What process technology is named, and is the design chiplet-based or monolithic?
- Customization and upgrade path: What flexibility is promised, and what upgrades have actually been demonstrated?
- Deployment timing: Is a vehicle application scheduled, confirmed for production, or already shipping?
Applied to the Honda-Renesas plan, the role, chiplet approach, named 3-nm process, target figures, and intended late-2020s vehicle timing are stated. Final production specifications, detailed benchmark conditions, and a confirmed delivery milestone are not established in the cited materials.
How the separate Mythic announcement relates
In February 2026, Honda announced separate SoC research and co-development with U.S.-based Mythic, focused on neuromorphic technology, including analog compute-in-memory. That announcement does not say the Mythic work replaces or changes the Renesas agreement. The available announcements do not establish how the two efforts may relate in future vehicles.
Quick Recap
What is known—and what remains open
- Announced: A Honda-Renesas development agreement for a high-performance SoC intended for future Honda 0 Series SDVs.
- Described design: Renesas Gen 5 R-Car X5 paired with a Honda-optimized AI accelerator using chiplets and named automotive 3-nm process technology.
- Stated targets: 2,000 TOPS based on a sparse AI model and 20 TOPS/W, with the TOPS estimate attributed to Renesas as of January 2025.
- Still unconfirmed in the cited materials: Final specifications, production measurements, the project’s current milestone status, and a confirmed delivery date.
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