RISC-V is becoming a serious architectural option for software-defined, electrified and increasingly AI-enabled vehicles—but it is not a single chip, a replacement already installed across production cars, or a guarantee of lower cost. It is an open instruction-set architecture (ISA) that lets different companies build automotive processors, microcontrollers, accelerators and system-on-chips. The strongest near-term opportunities are selected controllers, safety islands, custom accelerators and specialized compute, while software maturity, functional-safety evidence, cybersecurity and production qualification still determine whether a design can ship.
The European automotive shift was outlined by RISC-V International in an article published May 16, 2025 and updated June 12, 2025: “Automotive Industry Charts New Course with RISC-V”. Its panel included executives from Infineon Technologies, Codasip, Resiltech, Quintauris and CARIAD, moderated by Cortus’s Michael Chapman.
What RISC-V actually is
RISC-V is an ISA: the specification describing instructions, registers and related architectural behavior that software uses to control a processor. RISC-V International maintains and ratifies the standard. It does not manufacture chips, sell processor cores or provide a complete vehicle platform.
IP companies and semiconductor manufacturers implement the ISA in processor cores, MCUs, SoCs, vector units and AI accelerators. A chip may combine a standard RISC-V base with ratified extensions, vendor-specific instructions and automotive peripherals. “Open” means the standard is available under RISC-V International’s governance model and is not controlled by one silicon vendor. It does not mean every core, chip, compiler, safety package or development tool is free or open source. See the organization’s automotive overview.
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It is also useful to separate four layers: the ISA, a processor core implementing it, a SoC or MCU containing that core and peripherals, and the ECU or vehicle system in which the chip is deployed. Portability at the first layer does not make complete platforms interchangeable.
Why automakers are reconsidering processor architecture
Software-defined vehicles
Vehicles are consolidating functions into domain and zonal controllers, with software updates and long service lives becoming central to the product. A common, adaptable ISA can help preserve software and engineering expertise across processor generations, although peripheral, memory, interrupt, security and accelerator differences still require platform work.
Electrification
Battery management, inverter control, charging, thermal systems and power electronics all need efficient, deterministic embedded compute. A designer can tailor a RISC-V implementation to a narrow control workload rather than accept every feature on a generic processor roadmap.
ADAS, autonomy and AI
Driver assistance and automated-driving systems combine real-time control CPUs with GPUs, vector engines, neural accelerators and independent monitoring. RISC-V’s extensibility is relevant to that heterogeneous mix, but it does not make an AI accelerator a substitute for deterministic control, redundancy or validated fallback behavior.
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Long programs and technology sovereignty
Vehicle programs commonly outlast individual semiconductor roadmaps. Multiple potential IP and silicon suppliers can improve negotiating leverage and architecture-level optionality. That is different from guaranteed supply independence: foundries, memory, packaging, EDA, software, certification and geopolitical conditions remain dependencies.
Where RISC-V could appear in a vehicle
RISC-V International describes a range extending from low-power embedded control to centralized compute. Possible applications include:
- Body-control modules, actuator control and sensor hubs
- Battery-management, powertrain and power-conversion controllers
- Chassis, braking and steering subsystems
- Gateway, communications and zonal controllers
- Safety islands that monitor higher-performance processors
- Instrument clusters, digital cockpits and infotainment support
- ADAS perception, sensor fusion and machine-learning accelerators
- Central vehicle computers and secure-boot or cryptographic functions
This is an architectural opportunity map, not evidence that every listed function is already deployed in a RISC-V production ECU. RISC-V can also coexist with Arm, proprietary DSPs, GPUs and NPUs in one heterogeneous vehicle.
The technical case—and its limits
Modularity and custom instructions
Standard extensions can target vector processing, virtualization, real-time behavior and cryptography; custom extensions can accelerate a tightly defined workload. That can improve performance per watt, latency or silicon efficiency when the implementation, memory system and software are designed together.
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Customization has a cost. Code using one supplier’s instructions may not move cleanly to another core. Teams should prefer common profiles where portability matters and isolate proprietary extensions behind stable software interfaces where differentiation is necessary.
Power, performance and area
RISC-V can let a designer allocate silicon to the actual workload instead of following a one-size-fits-all processor roadmap. Potential benefits include predictable latency, smaller implementations and specialized acceleration. They are not guaranteed product results: process node, caches, memory bandwidth, compiler quality, thermal design, safety hardware and validation often dominate system performance.
Software reuse without false promises
A shared ISA can support reuse of compilers, debuggers, operating-system ports, middleware and engineering skills. It does not promise binary compatibility across all RISC-V processors. Boot firmware, peripherals, interrupt controllers, privilege configuration, RTOS ports, security hardware and custom accelerators can still force substantial porting and qualification.
Safety and cybersecurity are implementation questions
RISC-V itself is not automatically ISO 26262-certified because the ISA is open. Certification and a vehicle safety case attach to a particular core, chip, toolchain, development process and system. Automotive programs may require:
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- ISO 26262 processes and evidence for the applicable ASIL target
- ISO/SAE 21434 cybersecurity engineering
- Deterministic real-time behavior and freedom from interference
- Memory protection, privilege separation and fault detection
- Secure boot, authenticated firmware and protected over-the-air updates
- Diagnostics, trace, tool qualification, safety manuals and certification artifacts
- AUTOSAR or other production software integration and long-term maintenance
A processor IP block advertised as suitable for safety applications is not the same as a chip developed under a certified process, and neither is the same as a qualified ECU or complete vehicle system.
AI and ADAS: promising, but not a shortcut
Automotive AI must operate within tight power, thermal, cost, latency and reliability limits. RISC-V’s AI discussion emphasizes that “a car is not a cloud”; vehicle compute needs different trade-offs from data-center infrastructure. The RISC-V AI opportunities and challenges paper links successful deployment to software frameworks, model tooling, memory bandwidth, standards and safety evidence—not just an ISA.
In a practical architecture, vector or neural hardware may handle perception and prediction while independently monitored processors run bounded control loops. AI output should not automatically receive final authority over braking, steering or power delivery without the surrounding safety architecture, diagnostics and fallback paths.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Europe’s strategic role
The European Commission’s digital vehicle ecosystem initiative includes work on open-source building blocks, interfaces and tools for software-defined vehicles, alongside a pre-competitive RISC-V-based automotive hardware platform with AI capability. Those programs support European competitiveness, shared infrastructure and technology sovereignty.
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A public research or pre-competitive platform is evidence of strategic interest, not proof of a mass-market vehicle using an all-RISC-V compute stack. Commercial roadmaps, demonstration hardware, production-intent designs and volume deployment should be treated as separate maturity levels.
What adoption evidence exists?
Infineon’s roadmap
RISC-V International’s 2025 annual report says Infineon’s automotive MCU roadmap would be fully based on RISC-V and describes work on a standard MCU profile. An earlier Infineon-focused announcement described the effort more cautiously as an expansion of its automotive MCU portfolio for the next 5–10 years and beyond. The stronger statement should therefore be understood as RISC-V International’s account, not as independently verified market-wide deployment.
Tools and development platforms
IAR advertises automotive development tools supporting RISC-V alongside Arm, RH850, RL78, STM8 and other architectures, with AUTOSAR and MCAL integration: IAR automotive tools. Pricing is quote-based rather than publicly listed on the referenced page.
Microchip’s Mi-V ecosystem includes PolarFire SoC FPGAs with a five-core, 64-bit RISC-V processor and mixed real-time/Linux support. That is useful development hardware, not proof of a production automotive ECU or vehicle deployment.
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- ISA capability and ratified extensions
- Announced processor IP
- Development board or FPGA platform
- Automotive-qualified silicon
- Production-intent design
- Volume production
- Confirmed vehicle deployment
Public material establishes substantial ecosystem activity and commitments, but it does not establish RISC-V market share in production vehicles, a specific all-RISC-V car or superior automotive benchmark performance versus Arm.
RISC-V compared with established architectures
| Criterion | RISC-V | Established proprietary architecture |
|---|---|---|
| Governance | Open standard with multiple implementers | Controlled by an architecture owner |
| Customization | Strong extension model | Usually more constrained or vendor-specific |
| Ecosystem maturity | Growing and uneven by segment | Broad, established automotive workflows |
| Safety evidence | Depends on individual cores, tools and processes | Often more mature and widely deployed |
| Supplier choice | Potentially broad, subject to compatible products | May be concentrated but commercially mature |
| Software portability | Good at ISA level; not automatic at platform level | Supported by mature vendor ecosystems |
| Migration risk | New qualification and software work may be required | Existing investments can reduce transition risk |
| Differentiation | Greater freedom for custom silicon | Faster access to established roadmaps |
How an OEM or Tier 1 should evaluate a RISC-V design
Score the complete program, not just the instruction set:
- Technical: performance, latency, power, thermal envelope, memory bandwidth, determinism, vector/accelerator support, virtualization, debug and trace, networks and peripherals.
- Safety and security: ASIL target, safety mechanisms, freedom from interference, secure boot, update security, diagnostics, tool qualification and available safety evidence.
- Software: Linux, AUTOSAR and RTOS support; compiler quality; MCAL and middleware; portability across suppliers; cybersecurity maintenance.
- Commercial: IP licensing, NRE and verification cost, qualified silicon, foundry and packaging options, second-source feasibility, vendor stability and 10-year-plus support.
- Program risk: determine whether the offering is shipping, sampling, announced or experimental; document every custom extension; avoid dependence on one compiler, debugger or supplier.
What could slow adoption
- Fragmentation from incompatible custom extensions and profiles
- Higher migration, verification and certification costs than expected
- Gaps in automotive-grade middleware, trace, diagnostics and tool qualification
- Unproven performance or thermal behavior for a particular workload
- Long vehicle design cycles and cautious supplier qualification
- Continued dependence on foundries, EDA, memory, packaging and software vendors
RISC-V can reduce dependence on one ISA owner, but it cannot by itself eliminate vendor lock-in. A software stack, safety case or custom extension can still bind a program to one implementation.
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