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Several RISC-V processor IP options target automotive functional-safety designs, including SiFive’s Automotive E6-A/E7-A, Andes’ N25F-SE and newly certified D23-SE, and Fraunhofer IPMS’s EMSA5-FS. But RISC-V itself is not ASIL B certified: ISO 26262 claims apply to a specific implementation and its defined scope, while the vehicle-level safety case also depends on integration, software and system evidence. AI can support monitoring and anomaly detection, but deterministic safety mechanisms must retain final authority over safety-critical actions.
Is RISC-V itself certified for ISO 26262?
No. RISC-V is an open instruction-set architecture, not a processor implementation. As RISC-V International puts it, “No ISA is certified. The ISA is certifiable; implementations are certified.” A claim about ASIL capability or certification therefore needs to identify the particular processor IP, product, safety process or system and explain the scope covered.
RISC-V International describes automotive implementations across low-power microcontrollers, zonal controllers and central compute. An implementation can be designed to support an ISO 26262 safety target, but a processor core’s claim does not by itself establish that a complete ECU or vehicle function meets that target. The integrator still has to assess the documentation, diagnostics, software and system-level evidence relevant to its own safety case.
Which RISC-V cores explicitly target ASIL B?
The published claims differ in wording and scope. The table separates an explicit certification announcement from product-page support statements and development positioning; those should not be treated as interchangeable.
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- ESP32-P4-NANO development board based on ESP32-P4 chip, high-performance MCU with RISC-V 32-bit dual-core and single-core processors. 128 KB HP ROM, 16 KB LP ROM, 768 KB HP L2MEM, 32 KB LP Static RAM, 8 KB TCM. 32MB PSRAM in the chip's package, with onboard 16MB Nor Flash
- Onboard ESP32-C6-MINI module to extend 2.4GHz Wi-Fi 6 and Bluetooth 5/BLE for ESP32-P4, using SDIO interface protocol for communication, stable connection and efficient transmission. Reserved PoE Module header, more flexible for Power Supply
- Commonly used peripherals such as MIPI-CSI, MIPI-DSI, USB 2.0 OTG, Ethernet, SDIO 3.0 TF card slot, microphone, speaker header and RTC battery header, etc. Adtaping 2*2*13 GPIO headers with 28 x programmable GPIOs
- Powerful image and voice processing capability. Provides image and voice processing interfaces including JPEG Codec, Pixel Processing Accelerator, Image Signal Processor, H264 encoder
- Security features: Secure Boot, Flash Encryption, cryptographic accelerators, and TRNG. Additionally, hardware access protection mechanisms help to enable Access Permission Management and Privilege Separation
| Core | Published safety claim | Safety features described | AI or compute features described | Stated application context |
|---|---|---|---|---|
| SiFive Automotive E6-A / E7-A | SiFive’s official family pages list ISO 26262 ASIL B, ASIL D and split-lock support. The specific certificate scope is not stated in the supplied product information. | Split-lock support is listed; other diagnostic coverage details are not stated in the supplied product information. | Vector, matrix or AI-extension details are not stated in the supplied product information. | ADAS/AD, IVI, body, zonal, powertrain, central compute and safety-island applications. |
| AndesCore D23-SE | Andes announced on 2026-08-18 that the processor achieved ISO 26262 ASIL-B and ASIL-D certification with full compliance. The announcement identifies it as a Safety Element out of Context (SEooC). | Specific redundancy, lockstep, ECC, MPU and diagnostic-coverage details are not stated in the supplied announcement. | Andes describes vector processing, DSP capabilities, its Automated Custom Extension framework and an end-to-end AI hardware/software stack. | Safety-oriented processor IP; the announcement does not specify the full set of target vehicle domains. |
| AndesCore N25F-SE | Andes’ product page states support for ISO 26262 ASIL B functional safety for automotive applications. A more specific certification scope is not stated in the supplied product information. | Specific mechanisms are not stated in the supplied product information. | AI acceleration details are not stated in the supplied product information. | Automotive functional-safety applications. |
| Fraunhofer IPMS EMSA5-FS | Fraunhofer IPMS positions the core for ISO 26262 functional-safety development up to ASIL D; this is development positioning, not a stated certification of a complete vehicle system. | Integrated dual-mode or triple-mode redundancy, optional lockstep, bus ECC, configurable memory-protection unit, privilege modes, and reset and safety-manager modules. | AI-specific acceleration details are not stated in the supplied product brief. | 32-bit, in-order, five-stage RISC-V processor for safety-oriented designs. |
These entries are not a like-for-like ranking. The D23-SE announcement makes a dated certification claim and identifies an SEooC; the N25F-SE page states ASIL B support; SiFive’s family pages list ASIL levels and split-lock support; and Fraunhofer IPMS describes a core intended for safety development up to ASIL D. Ask each supplier what exact artifacts and activities its claim covers before using it to support a project decision.
Can AI run on a safety-critical automotive microcontroller?
AI can be part of an automotive design, but the safety role assigned to it matters. RISC-V International describes AI as able to “inform and monitor through anomaly detection, plausibility checks, and predictive maintenance while a deterministic mechanism retains final authority.” In practice, that means an AI task may flag a condition or provide an input for a safety decision, while a bounded, deterministic mechanism remains responsible for the safety-critical control action.
Rank #2
- CanMV-K230 is a credit card-sized development board for AI and computer vision applications based on the Kendryte K230 dual-core C908 64-bit RISC-V processor with built-in KPU (Knowledge Process Unit) and various interfaces such as MIPI CSI inputs and Ethernet.
- Shipping List(Basic Kit): 1* CanMV-K230, 1* Camera, 1* Type-C Cable for Power / Debug, 1* 2.4G/5G Antenna
- SoC: Dual-core C908. High-performance AI acceleration unit (KPU), AI performance is 13.7 times that of K210
- AI multi-modal: vision/speech/OCR/translation NMT support, and complete AI development tools
- Support RVV1.0. Support Three 4K HD camera inputs. Integrated DPU Full HD 3D depth engine, supports 1080P resolution
Andes describes vector and DSP capabilities, custom extensions and an end-to-end AI hardware/software stack for D23-SE. Those capabilities can be relevant to workloads that process sensor or vehicle data, but an AI stack or accelerator is not, by itself, evidence of functional-safety compliance. The safety case must account for how the AI workload is contained, monitored and prevented from overriding the deterministic safety path.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How should automotive teams compare these cores?
Start with the safety goal and system architecture, then compare evidence against the role the processor will actually play. A core suitable for a safety island may not be the right fit for a high-throughput ADAS workload, and a broad ASIL statement is not enough to establish integration suitability.
Rank #3
- Equipped with 32-bit RISC-V processor, up to 240MHz main frequency. Integrated with 384KB Static RAM, 320KB ROM, and 4MB Flash
- Integrated 2.4GHz and 5GHz dual-band Wi-Fi, Bluetooth 5 (LE), and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communications, with outstanding RF performance
- Onboard antenna switching chip, supports onboard antenna or external antenna (IPEX-1). USB Type-C port, easier to use
- Castellated module allows soldering directly to carrier boards, with rich peripheral interfaces
- Supports multiple low-power operating modes, enabling flexible adjustment of the balance between communication range, data rate, and power consumption to meet the power requirements of various application scenarios
- Pin down the claim. Ask whether the evidence covers the processor IP, an SEooC, a safety process or a larger product, and which ASIL level and operating assumptions it addresses.
- Review mechanisms and diagnostics. Look for the documented use of redundancy, lockstep, ECC, memory protection, fault detection and diagnostic coverage. A feature name alone does not show which faults are detected or how the design responds.
- Check real-time behavior. Establish whether the interrupt, memory and execution architecture supports the required deterministic timing for the intended safety function. The product descriptions summarized here do not provide comparable timing figures.
- Separate AI throughput from safety behavior. Identify any vector, matrix, DSP or custom-extension capabilities, then determine how the AI task is isolated from deterministic control and what happens when its output is invalid or unavailable.
- Request integration artifacts. Review the safety documentation, tools, assumptions and integration guidance that the supplier makes available, and confirm what is needed to build the project’s own safety case.
- Evaluate fit and commercial terms. Compare target domain, area, power and performance against the ECU constraints. The cited product information does not establish comparable area, power or performance figures, or licensing and support terms; obtain those directly from the supplier.
Because the published information summarized here does not establish a common test basis for determinism, performance, diagnostic coverage or commercial terms, those items need supplier-specific evidence rather than inference from the ASIL label.
Quick Recap
Best Value
- ESP32-C6FH8 Processor: Equipped with a high-performance 32-bit RISC-V processor with clock speed up to 160 MHz, and a low-power 32-bit RISC-V processor with clock speed up to 20MHz. Powerful AI Computing Capability & Reliable security features. It is suitable for the quick development of the HMI and other ESP32-C6 applications. ( with Pre-Soldered Header Version)
- 1.47inch Touch Display: Onboard 1.47inch IPS Capacitive Touch LCD display, 172x320 resolution, 262K color. Integrated AXS5106L capacitive touch chip, supports high-sensitivity touch operation, fast response speed and long life.
- Wire-less Communication: Supports 2.4GHz W-F-i 6 (802.11 ax/b/g/n) and Blue-tooth 5 (LE), with onboard antenna. Built-in 320KB ROM, 512KB HP SRAM, and 16KB LP SRAM, integrates 8MB Flash.
- Extensions and Interfaces: Adapting multiple GPIO interfaces, supports full-speed USB standard, facilitates peripheral connection and debugging. Onboard TF card slot for external TF card storage of pictures or files.
- Low Power Mode: Supports accurate control such as flexible clock and multiple power modes to realize low power consumption in different scenarios.
Rank #4
- 【High-Performance RISC-V Core】 CH32V003F4P6 microcontroller; 48MHz clock speed; 32KB flash memory; 4KB RAM; Suitable for embedded applications
- 【Flexible Power Supply Options】 Operates from 2.4V to 5.5V; supports 3.3V or 5V VDD; suitable for various power sources
- 【for Arduino and for Raspberry Pi Compatibility】 Programmable with for Arduino IDE; compatible for for Raspberry Pi; easy integration with common development platforms
- 【Low-Power Design for IoT Applications】 1.8µA sleep mode current; 72-hour operation with 2000mAh battery; efficient for battery-powered systems
- 【16 General-Purpose I/Os for Expandable Projects】 16 I/O pins available; includes IN+ and GND terminals; supports custom circuit connections and peripheral integration
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